DM54LS164 registers equivalent, 8-bit serial in/parallel out shift registers.
Y Gated (enable disable) serial inputs Y Fully buffered clock and serial inputs Y Asynchronous clear Y Typical clock frequency 36 M.
These 8-bit shift registers feature gated serial inputs and an asynchronous clear A low logic level at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse thus providing complete control.
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